In a typical active matrix display each pixel is provided with a transistor, more particularly a thin film field effect transistor (TFT, FET) which is used to control the appearance of the pixel. Broadly speaking, the gate connection of the FET is connected to a select line to select the pixel for writing data, and one of the source and drain of the FET is connected to a data line for writing data to the pixel, the other being connected to a pixel electrode for driving the display medium. In some types of display, in particular electrophoretic displays the pixel electrodes are located on one face of the display medium and a common electrode is provided covering the opposite face of the display medium thereby enabling an electric field to be provided across the display medium, for example to switch the device from one display state, say white, to another say black (or vice versa). The skilled person will appreciate that pixel circuits may in practice be more complex than this, but the same general features remain.
One problem in such displays is parasitic capacitance between the gate and pixel electrodes; in an electrophoretic display this can be exacerbated by the presence of the common pixel electrode, which is used to provide a bigger pixel capacitance. A consequence of this parasitic capacitance is that the voltage applied to a pixel electrode ends up being different to the voltage applied to the corresponding data line of the display, the actual pixel voltage being off set from that applied. This is, in effect, a side effect of the parasitic capacitances in the display when the gate connection is on, and this “kickback” has a deleterious effect on the visual appearance of the electrophoretic display.
WO 2005/020199 describes an electrooptic display with a writing mode and a non-writing mode, the display being arranged to apply a first voltage to the common electrode when the display is in its writing mode and a second voltage, different from the first voltage, when the display is in its non-writing mode. In embodiments (FIGS. 4 and 5) a sensor pixel approach is described, the purpose of these pixels being to provide an indication of the required feedthrough voltage; in another embodiment (FIG. 9) an approach is described which uses an internal adjustment which does not require the presence of sensor pixels, instead substituting a capacitor. In a still further embodiment (FIG. 10) a controller is used to control the voltage offset between the voltage applied to the common electrode when the display is in its non-writing mode (VSM) and the voltage applied to the common electrode when the display is in its writing mode (VCOM). Other systems are described in US2007/211006, US2008/198122, US2009/040412 and WO2005/020199.
Background prior art can be found in WO2011/064578 and WO2005/020199.
We have previously described, in WO/2011/064578, techniques for compensating gate kickback which offset a value of a common voltage on the common electrode by an offset value dependent on a difference between a magnitude of a positive gate voltage and a magnitude of a negative gate voltage.
We now describe improved techniques for compensating gate kickback.